1. Field of the Invention
This invention relates to a serial data input system that receives and stores data serially transferred from an external circuit.
2. Description of the Related Art
Conventionally, a digital camera and the like are provided with a serial data input system that receives and stores display data serially transferred from an external circuit such as a microcomputer. FIG. 12 is a block diagram showing such a serial data input system. The serial data input system has an interface circuit 10 and a serial data input register 20.
A clock CL, a chip enable signal CE and data DI (display data SDI and 8-bit address data A0-A7 that is serially transferred ahead of the display data SDI in synchronization with the clock CL) serially transferred from a microcomputer are inputted to the interface circuit 10.
And the interface circuit 10 outputs the display data SDI and the clock CL without modification only when the address data A0-A7 coincides with inherent IC address data that has been stored in the interface circuit 10 in advance. The clock CL outputted from the interface circuit 10 is hereafter referred to as a clock SCL.
The display data SDI is inputted to and shifted in the serial data input register 20 in synchronization with the clock SCL that is outputted from the interface circuit 10. The serial data input register 20 is composed of a group of serially connected four shift registers 21, 22, 23 and 24, each composed of eight D-FF circuits (Delay Flip-Flop circuits), as shown in FIG. 13. The clock SCL is applied to all of the D-FF circuits.
An operation of the serial data input system described above will be explained hereinafter referring to a timing chart shown in FIG. 14. When the address data A0-A7 transferred from the microcomputer coincides with the inherent IC address data and the chip enable signal CE rises to a high level, the interface circuit 10 outputs the clock SCL and 32 bits of the display data D0-D31 are inputted to and sequentially shifted in the group of shift registers 21-24 in the serial data input register 20 in synchronization with a rising edge of each clock pulse of the clock SCL. Each of output data SD31 -SD0 is retained at a Q terminal of corresponding each of the D-FF circuits that constitute the group of shift registers 21-24. The 32 bits of display data D0-D31 are inputted to the serial data input register 20 as described above. Technologies related to the interface circuit 10 are disclosed in Japanese Patent Application Publication No. 2005-94694.
In the serial data input register 20, however, a through-current for re-writing the data flows in every D-FF circuit at every clock pulse of the clock SCL when the display data D0-D31 is serially inputted, since the group of four shift registers 21, 22, 23 and 24 are serially connected and the clock SCL is applied to all of the D-FF circuits. Therefore, the more number of bits (the number of the D-FF circuits) are in the serial data input register 20, the more through-current flows between the power supply and the ground in each of the D-FF circuit, causing a problem that the power consumption in the whole system increases as a result. Also, a lot of effort is required to meet EMC (Electromagnetic Compatibility) requirements, since a power supply noise increases as the through-current increases.
In addition, since the number of D-FF circuits disposed in the IC chip as well as wirings connecting between the D-FF circuits increase as the number of bits in the serial data input register 20 increases, a difference in delay time of the clock SCL, or a clock skew, becomes more likely to be caused between D-FF circuits, thus malfunctioning of the D-FF circuits may be caused. Therefore, a lot of time and effort are required to prevent the clock skew.